The present invention relates to microelectronic packaging of semiconductor chips and, more specifically, to the process of manufacturing IC flip chip assemblies designed to reduce the structural damage to C4 interconnections due to thermal stress and the CTE mismatch of the chip and the packaging material.
Advances in microelectronics technology tend to develop chips that occupy less physical space while performing more electronic functions. Conventionally, each chip is packaged for use in housings that protect the chip from its environment and provide input/output communication between the chip and external circuitry through sockets or solder connections to a circuit board or the like. Miniaturization results in generating more heat in less physical space, with less structure for transferring heat from the package.
The heat of concern is derived from wiring resistance and active components switching. The temperature of the chip and substrate rises each time the device is turned on and falls each time the device is turned off.
As the chip and the substrate ordinarily are formed from different materials having different coefficients of thermal expansion (CTE), the chip and substrate tend to expand and contract by different amounts, a phenomenon known as CTE mismatch. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and printed wiring board (PWB) and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause fatigue of the electrical interconnections. This is especially true for the solder ball of the controlled collapse chip connection, also known as xe2x80x9cC4xe2x80x9d, connections. It is therefore important to mitigate the substantial stress caused by thermal cycling as temperatures within the device change during operation.
One type of semiconductor chip package includes one or more semiconductor chips mounted on a circuitized surface of a substrate (e.g., a ceramic substrate or a plastic composite substrate). Such a semiconductor chip package is usually intended for mounting on a printed circuit card or board. In the case of a ball grid array (BGA) package, the chip carrier includes a second circuitized surface opposite the surface to which the chip is attached. This, in turn, is connected to the printed circuit card or board.
Chip carriers of this type provide a relatively high density of chip connections and are readily achieved by mounting one or more semiconductor chips on the circuitized surface of a chip carrier substrate in the so-called xe2x80x9cflip chipxe2x80x9d configuration.
Flip chip bonding is described by Charles G. Woychik and Richard C. Senger, xe2x80x9cJoining Materials and Processes in Electronic Packagingxe2x80x9d in PRINCIPLES OF ELECTRONIC PACKAGING, by Donald P. Seraphim, Ronald Lasky and Che-Yu Li, McGraw-Hill Book Company, New York, N.Y. (1988), at pages 577 to 619; and by Nicholas G. Koopman, Timothy C. Reiley, and Paul A. Totta, xe2x80x9cChip-To-Package Interconnectionsxe2x80x9d in MICROELECTRONIC PACKAGING HANDBOOK, by Rao R. Tummala and Eugene Rymaszewski, Van Nostrand Reinhold, New York, N.Y. (1988), at pages 361 to 453.
Flip chips are small semiconductor dies having terminations all on one side of the entire face of the die in the form of a pattern of solder pads or bump contacts. These solder bumps are deposited on solder wettable terminals on the chip. Typically, the surface of the chip has been passivated or otherwise treated. In this way the use of a flip chip package allows full population area arrays of I/O. The flip chip derives its name from the practice of flipping or turning the chip over after manufacture, prior to attaching the chip to a matching substrate.
As described by Seraphim et al. and Tummala et al., an electronic circuit contains many individual electronic circuit components: thousands or even millions of individual resistors, capacitors, inductors, diodes, and transistors. These individual circuit components are interconnected to form the circuits. The individual circuits are interconnected to form functional units. Power and signal distribution are performed through these interconnections. The individual functional units require mechanical support and structural protection. The electrical circuits require electrical energy to function and the removal of thermal energy to remain functional. Microelectronic packages such as chips, modules, circuit cards, circuit boards, and combinations thereof are used to protect, house, cool, and interconnect circuit components and circuits.
In the flip chip configuration, the chip or chips are mounted active-side-down on solderable metal pads on the substrate using solder balls, a C4 connection, a gold bump, or a conductive epoxy.
Controlled collapse chip connection in flip chip technology has been successfully used for about 30 years for interconnecting high I/O count and area array solder bumps on the silicon chips to the base ceramic chip carriers (e.g., alumina carriers). In the C4 process, as distinguished from the flip chip process, the solder wettable terminals on the chip are surrounded by ball limiting metallurgy (BLM), and the matching footprint of solder wettable terminals on the card is surrounded by a solder mask. These structures act to limit the flow of molten solder during reflow.
Bonding can be used in an unpackaged configuration known in the art as direct chip attach (DCA): the direct connection of a chip to a card or board without an intermediate layer of packaging. The combination of a chip mounted on an intermediate carrier is usually described as the Afirst level package@. DCA can be a lower cost method of connecting a chip to a card, since the first level package is thereby eliminated.
For direct chip attach, individual IC chips are mounted on the cards or boards. The space between the mounted chip and the card or board is then filled with an epoxy resin. By this expedient, the standoff between the IC chip and the card or board is encapsulated with epoxy.
If a polymeric dielectric card or board is employed, the DCA process requires low temperature solder metallurgy. Moreover, direct chip attach, when used with an underfill, increases the fatigue resistance of the C4 solder interconnections to thermal cycling, acts as an alpha emission barrier to MOSFET memory chips, is a parallel thermal path for heat dissipation, and provides physical protection to the chips and C4 solder interconnections.
However, one problem encountered with the combination of DCA and C4 bonding is the difficulty of reworking the encapsulated package. In order to improve rework and to accommodate the CTE mismatches between the chip and the PWB, many prior art proposals have been developed to connect integrated circuit chips to printed wiring boards via an intermediate element. Often, chip carriers are interposed between the chip and the circuit board; the CTE of the chip carrier is itself chosen as some intermediate value to provide a reasonable match to both the chip and to the printed circuit board. The very large difference in CTE between the silicon device and the printed circuit board generally requires some intermediate device carrier. One such type of interconnection mounts the integrated circuit chip on a ceramic chip carrier or module, which module is mounted on a circuit board. One or more chips may be mounted on each device carrier or module, and one or more modules may be mounted on any given circuit board. In a particularly well known type of configuration, the integrated circuit chip is mounted onto a ceramic module by flip chip bonding wherein the I/O pads on the face of the chip are bonded to corresponding pads on the module. Such connections are formed by solder bumps or solder balls normally using solder reflow techniques. It is these connections that are referred to as C4 connections.
Most conventional single and multiple chip packages are typically constructed from thick, mechanically robust, dielectric materials, such as ceramics (e.g., alumina, aluminum nitride, beryllium oxide, cordierite, and mullite) and reinforced organic laminates (e.g., epoxies with woven glass, polyimides with woven glass, and cyanate ester with woven glass). In some cases, materials are combined to produce certain improved properties. For example, a package may have a ceramic base with one or several thin films of polyimides or benzocyclobutane (BCB) disposed thereupon.
In an attempt to overcome the problem of thermal mismatch between the chip carrier and the circuit board it has been proposed to fashion the chip carrier from a material similar to that of the circuit board. Such techniques are described in IBM Technical Disclosure Bulletin Vol. 33, No. 2, pages 15-16 and IBM Technical Disclosure Bulletin Vol. 10, No. 12, pages 1977-1978. However, both of these references require that the connections, at least for the signal I/O lines, be on the same side of the carrier as that to which the chip is mounted. These techniques do solve the problem of thermal mismatch between the chip carrier and the circuit board, but require peripheral I/O bonding and an additional interposer between the chip and the chip carrier. IBM Technical Disclosure Bulletin Vol. 10, No. 12 requires peripheral attachment of the chip to an interposer (carrier 2) which is bonded to the chip carrier and then attached to the card. This peripheral bonding on the chip limits the I/O that can be placed on a small chip.
As noted above, whether the chip is attached to a carrier or directly to the PWB, these structures are made of materials with coefficients of thermal expansion that differ from the CTE of the material of the semiconductor device: silicon. Normally the device is formed of monocrystalline silicon with a coefficient of thermal expansion of 2.5-3.0 ppm/EC. If the substrate is formed of a ceramic material, typically alumina with a coefficient of expansion of 5.5-6.5 ppm/EC, then the mismatch in thermal expansion is relatively small. The problem is exacerbated with less expensive substrate materials, such as fiberglass, that have a CTE of roughly 17 ppm/EC.
The stress on solder bonds during operation is approximately proportional to (1) the magnitude of the temperature fluctuations, (2) the distance of an individual bond from the neutral or central point (DNP), and (3) the difference in the coefficients of expansion of the material of the semiconductor device and the substrate. Stress is also inversely proportional to the height of the solder bond (i.e., the spacing between the device and the support substrate). The seriousness of the situation is further compounded by the fact that, as the solder terminals become smaller in diameter in order to accommodate the need for greater density, the overall height decreases.
In order to strengthen solder joints without affecting the electrical connection, the gap is filled with a polymeric encapsulant, typically a filled polymer. The encapsulant is typically applied after the solder bumps are reflowed to bond the integrated circuit die to the printed circuit board. A polymeric precursor is dispensed onto the board adjacent the die and is drawn into the gap by capillary action. The precursor is then heated and cured to form the encapsulant. This curing can also create stresses that can be detrimental to the die.
An improved solder interconnection structure with increased fatigue life was disclosed in U.S. Pat. No. 4,604,644 to Beckham, et al., assigned to the present assignee, disclosure of which is hereby incorporated by reference. The Beckham patent discloses a structure for electrically joining a semiconductor device to a support substrate that has a plurality of solder connections. Each solder connection is joined to a solder wettable pad on the device and to a corresponding solder wettable pad on the support substrate. Dielectric organic material is disposed between the peripheral area of the device and the facing area of the substrate. The material surrounds at least one outer row and column of solder connections but leaves the solder connections in the central area of the device free of dielectric organic material.
Other prior art solutions make use of an underfill material disposed between the chip and the supporting substrate in an attempt to redistribute the stress caused by CTE mismatch. Without the underfill material, this stress is wholly borne by the solder balls. The underfill material allows this stress to be more uniformly spread out over the entire surface of the chip, supporting substrate and solder balls. Examples of the use of underfill materials may be found in U.S. Pat. Nos. 5,194,930, 5,203,076, and 5,249,101.
After soldering the IC to the substrate, an epoxy resin or other material is inserted into the space between the IC and the substrate and acts as a glue. In addition to being inserted into the space, surface-tension produces a capillary action between the IC and the substrate that pulls the epoxy into the space. The epoxy is also pulled up along the sides of the IC by the surface tension. To make the mechanical bond of the epoxy even stronger, it is possible to roughen the surface of the substrate or the IC, chemically for instance, before applying the epoxy underfill.
An epoxy, after being introduced under capillary action into a space provided between the semiconductor chip and the package substrate, is cured and hardened. The hardened epoxy acts to bond the semiconductor chip to the package substrate and to protect the fragile solder connections.
The normal flow in a flip chip attach process is as follows: a) the die is fluxed; b) the die is placed on the substrate with bond pads on the die being aligned with bond pads on the substrate; c) solder is reflowed between bond pads on the die and substrate; d) the die is underfilled with a thermoset material; and e) the underfill material is fully cured.
Underfilling ensures minimum load on the interconnects and becomes the primary load bearing member between the chip and the substrate during thermal or power cycling induced due to the operation of the chip. Thermoset type materials are commonly used in the industry as underfill material. In order for the epoxy to bear much of the load it must be relatively rigid. As a result the chip and substrate are strongly coupled so that differential thermal expansion causes bending of the package when the temperature varies from that at which the epoxy was cured. In extreme cases this bending can cause cracking of the chip but, with proper design, this problem may be overcome. Without the epoxy this differential expansion causes shear in the C4 solder joints but little package bending. Warpage tends to be smaller when thicker organic substrates are used and greater as the rigidity and thickness of the substrate decreases.
Accordingly, it is a general object of the present invention to provide novel and useful semiconductor devices wherein the foregoing problems are mitigated.
One specific object of the present invention is to provide a package for the semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on the chip-to-substrate or chip-to-card interconnections.
Another object of the present invention is to provide a package that can be readily modified to changes in chip size and configuration.
Another object of the present invention is to design a package that allows adhesive or underfill to be applied after the package has been assembled.
In accordance with the present invention, there is provided an electrical package that includes a substrate with an upper surface, having at least one electrical circuitry connecting pad. An electric device is also provided with a first modulus of elasticity. The electric device has a connection region on its lower major surface. At least one flexible connector links the connecting pad(s) to the connection region. A collar is also provided with a second modulus of elasticity. The vertical side or dimension of the collar is shorter than the electric device perimeter and is bonded to the perimeter. The horizontal side or dimension of the collar is bonded to the substrate upper surface. The adhesive material has a third modulus of elasticity. Thus, a unitary electrical package is formed that includes the electric device, the substrate and the collar. The second modulus of elasticity is at least as large as the third modulus of elasticity.